The EV12AS200 is a 12-bit 1.5 GSps ADC. The device includes a front-end Track and Hold stage (T/H), followed by an analog encoding stage (Analog Quantizer) which outputs analog residues resulting from analog quantization. Successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuitry and a resynchronization stage followed by a DEMUX with 100Ω differential output buffers. It integrates 3 Wire Serial Interface (3WSI) circuit (write only), which can be activated or deactivated (via Mode signal). Main functions accessed via the 3WSI can also be accessed by hardware (OA, GA, SDA, SDAEN_n, TM_n, RS pin).
|EV12AS200 Application Note||EV12AS200 Application Note|
|BDC Checklist||BDC Checklist|
|Board Layout||Board Layout|
|Ev12as200xzpy Qualification Report||Ev12as200 Qualification Report|
|EV12AS200 DK Nov 12||EV12AS200 Demo Kit summary|
|EV12AS200AGS EB User Guide||EV12AS200AGS EB User Guide|
|EV12AS200ZPY EB User Guide||EV12AS200ZPY EB User Guide|
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