The first 12-bit ADC to feature a Cross Point Switch (CPS), the EV12AQ600 can operate its four cores simultaneously, independently or paired, to assign its 6.4 GSps sampling speed across the user’s desired channel count:
SFDR in 4 channels mode without H2 and H3 harmonics is better than 70 dBFS at -1 dBFS up to 5980MHz.
To help you evaluate and design with this ADC, we provide you with the following right here below:
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This exclusive tutorial video will give you a useful overview of a multi-ADC synchronization technique, from the needs of synchronous and deterministic behavior within a multi-channel system to a practical implementation in our Lab. The demo also features Teledyne e2v’s latest EV12AQ600 ADC.
| Nyquist Zone | Output level | ENOB | SFDR |
|---|---|---|---|
| NZ1 | -1dBFS | 8.7 bits | 71 dBFS |
| NZ2 | -1dBFS | 8.4 bits | 63 dBFS |
| NZ3 | -1dBFS | 8.1 bits | 64 dBFS |
| NZ4 | -8dBFS | 8.3 bits | 66 dBFS |
| NZ5 | -8dBFS | 8.2 bits | 67 dBFS |
| Nyquist Zone | Analog input bandwith selected | Channel mode | NPR |
|---|---|---|---|
| NZ1 | NFPBW | 4 | 44 dB |
| NZ2 | NFPBW | 4 | 43.5 dB |
| NZ3 | EFPBW | 4 | 43 dB |
| NZ4 | NFPBW | 1 | 42 dB |
| NZ5 | NFPBW | 1 | 42 dB |
| NZ6 | EFPBW | 1 | 40 dB |
| Document | Description | Type |
|---|---|---|
| ADX4 IP user guide | ADX4 IP user guide for implementation in a Xilinx Kintex Ultrascale FPGA | |
| Application Note AN 21S 218124 | Assembly recommendations | |
| Application Note AN 60S 217359 (A) | EV12AQ600 Overdrive in Cold Sparing Conditions | |
| Application Note AN 60S 218492 | How to improve EV12AQ600 ADC SNR performance using Simultaneous Sampling and Averaging | |
| Design Example | ADX4 Design Example User Guide | |
| EV12AQ600 Synchronization Chaining Technical Note | SYNCHRONIZATION CHAINING, Simplifying Multi-channel Synchronization in Gigahertz Data Converters. |
| Document | Description | Type |
|---|---|---|
| EV12AQ600 Datasheet | EV12AQ600 / EV12AQ605 Datasheet |
| Document | Description | Type |
|---|---|---|
| EV12AQ600-2ADC-EVM Synchronization Kit User Guide | Multi-chip Synchronization Board with X2 EV12AQ600 + FPGA | |
| EV12AQ600-ADX-EVM Demo Kit User Guide | Demonstration Board with EV12AQ600 + FPGA | |
| EV12AQ600-FMC-EVM Development Kit User Guide | Development Board with EV12AQ600 + FMC |
| Document | Description | Type |
|---|---|---|
| EV12AQ600 | EV12AQ600 ibis file | OTHER |
| Flyer | Product flyer | |
| MIL-PRF-38535 QML Class Y Flow | Description of the space flow applicable to EV12AQ600 for non-hermetic flip-chip devices. |
| Document | Description | Type |
|---|---|---|
| EV12AQ600 | Qualification Report | |
| EV12AQ600 TiD and SEE radiation report | J710JSG - TiD and SEE radiation Report |
| Document | Description | Type |
|---|---|---|
| ESIstream white paper | ESIstream IP – ease your way to deterministic data serialization |
FPGA Support - ESIstream website
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