This tutorial video explains how to create a Vivado project to implement ADX4 IP on a Kintex Ultrascale FPGA starting from a VHDL design example and using EV12AQ600-ADX-EVM demo board. This tutorial also delivers all steps to load the FPGA bitstream, retrieve sample data processed by the ADX4 IP using Vivado and analyze SFDR performance using a python Graphical User Interface (GUI).
For more info, please click the following links:
AX4 IP Teledyne SP Devices technical presentation and white paper
EV12AQ600-ADX-EVM demo kit user guide
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