Newsroom

  • Advanced optical digital harness (ODH) set to unleash novel multi-element microwave antennas
    2022/08/08 12:03 PM

    Links to transfer data, clock, configuration, and even system-wide synchronization signalling  marks the arrival of practical multi-element smart digital antennas Newsworthy pointers Streaming sample, control & configuration data, as well as refer…

    Read More
  • Fully-Digital Multi-Band SAR System operating at L, C, X and Ku Bands
    2022/07/22 2:29 PM

    This white paper has been written with the Partnership of ECHOES Radar Technologies.   Synthetic Aperture Radar (SAR) is an active imaging sensor employed in remote sensing applications that can achieve wide areas images in every weather condition. SAR imaging uses an antenna that is mounted on a moving platform. Through the processing of received echoes, SAR permits to obtain a larger syn…

    Read More
  • Demonstration of a microwave ADC and DAC Digital Optical Harness proof of concept for remote architecture
    2022/07/11 3:16 PM

    The first demonstration of an optical digital harness to connect remote microwave data converters to a central data processing unit, like a FPGA, replacing copper coax cables with optical fibers. With fiber, sample data, control signals, synchronization signal and reference clocks are routed over significantly longer distances, reducing weight and increasing data density compare to coax cable. Thi…

    Read More
  • Radiation Mitigation Techniques for Teledyne e2v’s Digital Processing Space Products
    2022/06/27 2:43 PM

    State-of-the-art radiation tolerant CPUs and Memories utilize design and fabrication techniques that are impacted by harsh radiation environments in Space. Single event effects (SEEs) arising from strikes from galactic cosmic rays, protons, or neutrons on these critical components, require radiation mitigation. Understanding and characterizing radiation-induced effects, within a particular radiati…

    Read More
  • Simulate EV12AQ600 ADC ESIstream serial interface
    2022/06/23 9:13 AM

    Learn how to simulate the EV12AQ600 ADC ESIstream serial interface using Vivado simulator and testbench available in each ESIstream package (KU FPGA, Versal ACAP…). Learn about synchronization aspects and what the overall latency is made of.   EV12AQ600 ADC product webpage     ESIstream web site Youtube video: G et started with the ESIstream serial interface of th…

    Read More
  • Moku:Pro software defined instrument leveraging EV10AQ190 ADC cross-point switch capability and best-in-class low frequency noise performance
    2022/06/20 2:33 PM

    This case study has been written with the Partnership of Kate Mueller from Liquid Instruments. Moku:Pro is a scalable, high-performance test solution for developing and validating next-generation devices and systems. It offers users flexibility and reconfigurability through software-defined instrumentation with 4 input and 4 output channels. Teledyne’s EV10AQ190 high speed and high precision…

    Read More
  • Demonstration of Teledyne e2v DDR4 with AMD XILINX Kintex Ultrascale FPGA
    2022/06/09 9:39 AM

    Generate the DDR4 controller IP to interface Teledyne e2v DDR4 products with AMD Xilinx devices. In this short video, you will learn how to setup the DDR4 controller IP to interface the Teledyne e2v DDR4 products with the programmable logic of XILINX devices. Watch this short video to see in practice th…

    Read More
  • Learn About ADX4 IP to Improve ADC RF Performance at Any Input Frequency and Temperature
    2022/06/09 9:35 AM

    This tutorial video explains how to create a Vivado project to implement ADX4 IP on a Kintex Ultrascale FPGA starting from a VHDL design example and using EV12AQ600-ADX-EVM demo board. This tutorial also delivers all steps to load the FPGA bitstream, retrieve sample data processed by the ADX4 IP using Vivado and analyze SFDR performance using a python Graphical User Interface (GUI). For more inf…

    Read More
  • Boost dynamic performance of a broadband ADC by some 10 dBFS instantly with spur reduction IP
    2022/06/07 4:26 PM

    Benefit from an immediate design-free, dynamic performance gain Newsworthy pointers • The new EV12AQ600/605-ADX4 device options now feature an integrated ADX4 license key enabling enhanced dynamics when operating at up to a peak of 6.4 GS/s (single channel mode). • ADX4 - a post-processing algorithm compatible with Xilinx Kintex…

    Read More
  • Start an ESIstream serial interface development with Versal ACAP and EV12AQ600 ADC
    2022/05/19 11:00 AM

    Get all information to accelerate your ESIstream high-speed serial interface development introducing the Versal ACAP ESIstream package based on the VCK190 Versal AI core development kit. The Versal ACAP ESIstream package will help you to get started with Versal ACAP and a high-speed data converter that uses the ESIstream serial interface, like EV12AQ600 ADC (FPGA ESIstream RX) and EV12DD700 DAC (…

    Read More
Join our Mailing List
Subscribe to email announcements
Our Latest Tweets
Follow us on Twitter
Connect With Us